1. Field of the Invention
The present invention relates to a method for manufacturing a dielectric memory having a capacitor element in a three-dimensionally stacked structure.
2. Description of Related Art
A ferroelectric memory is one kind of non-volatile memories in which ferroelectric materials are used. With advanced microstructure and higher-level integration of semiconductor devices in these days, the microstructuring of ferroelectric memories has been demanded. To microstructure a capacitor part, a micromachining technique is required.
However, the materials used for forming a ferroelectric capacitor, such as Pt, Ir, PZT, are very difficult to etch. Particularly, in the dry etching of Pt or Ir, residues called “fence” are generated in a resist forming process used in the LSI manufacturing process, and become an obstacle to the micromachining. Therefore, the dry etching of Pt or Ir uses a high-temperature dry etching process using a hard mask (see e.g. JP 2003-258201 A).
To make memory cells further finer, a capacitor of a three-dimensionally stacked structure, in which a dielectric capacitor is formed in a hole or a trench, is used as an approach to secure an area for a ferroelectric capacitor. This makes it possible to secure a larger overall area for a capacitor with a small projection area.
However, the inventors of the present application have found that when the above-mentioned conventional etching process using a hard mask is applied to such a ferroelectric capacitor of the three-dimensionally stacked structure, the following problems occur.
First, when a usual film forming method (e.g. sputtering) is used, in a hole or trench having a large aspect ratio, a film has significantly different film thicknesses on upper area, sidewall, and bottom of the hole or trench, respectively. This causes a hard mask on bottom of the hole or trench to have a film thickness smaller than a film thickness on outside areas of the hole or trench.
As a result, the following problem occurs. After depositing materials for a lower electrode, a ferroelectric film, and an upper electrode in the hole or trench, when the ferroelectric film and the upper electrode are subjected to etching using a hard mask, a portion of the hard mask on bottom of the hole or trench is etched also at the same time, thereby decreasing a film thickness. The decrease in the film thickness of the hard mask causes pin holes to be formed, which result in a problem that a chemical solution used in a later washing process remains in the hole or the trench, thereby damaging a capacitor, and decreasing the yield.
Further, there also is the following problem. When a hard mask is formed by etching using a resist process, the resist remains in hole or trench as particles, causing a decrease in the yield in a later process.